A 65nm 1V to 0.5V linear regulator with ultra low quiescent current for mixed-signal ULV SoCs

Author

de Streel, Guerric ; De Vos, J. ; Flandre, Denis ; Bol, David

Author_Institution

ICTEAM Inst., Univ. Catholique de Louvain, Louvain-la-Neuve, Belgium

fYear

2014

fDate

4-6 May 2014

Firstpage

1

Lastpage

4

Abstract

A linear regulator for point of load power delivery with 280nA quiescent current and 0.008mm² area is presented in this paper. Strong specifications on Power Supply Rejection Ratio (PSRR) and power consumption were included in the design at 0.5V output voltage to supply both low power analog and Ultra-Low-Voltage (ULV) digital circuits with a maximum load current of 0.5mA. Current mode pole splitting and NMOS source follower power stage allows us to optimize PSRR and guarantee stability whilst keeping low silicon footprint for the 6pf on-chip capacitor. We demonstrate its use for supplying a ULV CMOS imager that was manufactured in 65nm LP/GP CMOS process.

Keywords

CMOS analogue integrated circuits; CMOS digital integrated circuits; circuit stability; low-power electronics; mixed analogue-digital integrated circuits; power consumption; power supply circuits; system-on-chip; voltage regulators; LP-GP CMOS process; NMOS source follower power stage; PSRR; ULV CMOS imager; capacitance 6 pF; current 280 nA; current mode pole splitting; linear regulator; low power analog circuits; mixed-signal ULV SoCs; on-chip capacitor; power consumption; power supply rejection ratio; size 65 nm; ultra low quiescent current; ultra-low-voltage digital circuits; voltage 1 V to 0.5 V; Capacitance; Current measurement; MOS devices; Noise; Regulators; System-on-chip; Transient analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Faible Tension Faible Consommation (FTFC), 2014 IEEE

Conference_Location

Monaco

Type

conf

DOI

10.1109/FTFC.2014.6828597

Filename

6828597