DocumentCode
1507343
Title
Low-voltage CMOS four-quadrant multiplier
Author
Liu, Shen-Iuan ; Chang, Chen-Chieh
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
33
Issue
3
fYear
1997
fDate
1/30/1997 12:00:00 AM
Firstpage
207
Lastpage
208
Abstract
A new CMOS four-quadrant multiplier that can operate from supply voltages of ±1.5 V is presented. This circuit was fabricated in a standard 0.8 μm single-poly double-metal CMOS process. Experimental results show that the nonlinearity can be kept <2% across the entire differential input voltage range of ±0.8 V. The total harmonic distortion is <2% with the differential input range up to ±0.8 V. The measured 3 dB bandwidth of this multiplier is ~5 MHz. It is expected to be useful in low-voltage analogue signal processing applications
Keywords
CMOS analogue integrated circuits; analogue multipliers; -0.8 to 0.8 V; -1.5 V; 1.5 V; 5 MHz; CMOS four-quadrant multiplier; LV analogue signal processing applications; Si; THD; differential input voltage range; low-voltage multiplier; single-poly double-metal CMOS process; total harmonic distortion;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19970168
Filename
575924
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