A distortion reduction technique for bootstrapped-gate MOS Sample-and-Hold circuits using body-effect compensation

Author

Sen, Satyaki ; Shaik, K.A. ; Mukherjee, Jayanta ; Dhalvaniya, P.

Author_Institution

Int. Inst. of Inf. Technol. Bangalore (IIIT-B), Bangalore, India

fYear

2014

fDate

4-6 May 2014

Firstpage

1

Lastpage

4

Abstract

A distortion improvement technique for bootstrapped-gate Sample-and-Hold (S/H) circuits, is proposed. The gate overdrive voltage and conductance of the MOS sampling switch are made constant by cancelling the body-effect induced variations in the threshold-voltage. An amplifier is used to provide appropriate gain in the bootstrapped-gate path. The technique allows the minimized second-harmonic distortion (HD2) by adjusting the gain to Ag =1+kγ1, where kγ1 is the sensitivity of threshold voltage to the source voltage. Furthermore, the S/H distortion remains insensitive to the amplifier op-amp characteristics. Chip prototype measurement results of a single-ended S/H amplifier using 0.18 μm CMOS technology show HD2 improvement of 11 dB over conventional bootstrapped-gate S/H.

Keywords

CMOS integrated circuits; MOS analogue integrated circuits; bootstrap circuits; harmonic distortion; sample and hold circuits; CMOS technology; MOS sampling switch; body effect compensation; bootstrapped gate MOS sample and hold circuits; chip prototype measurement; distortion reduction technique; gate overdrive voltage; second harmonic distortion; size 0.18 mum; Bandwidth; CMOS integrated circuits; CMOS technology; Logic gates; Switches; Gate over drive (GOD); Sample-and-Hold (S/H) circuit; Spurious-Free-Distortion Ratio(SFDR); body-effect; conductnace(Gm); gate-boot-strapping;

fLanguage

English

Publisher

ieee

Conference_Titel

Faible Tension Faible Consommation (FTFC), 2014 IEEE

Conference_Location

Monaco

Type

conf

DOI

10.1109/FTFC.2014.6828613

Filename

6828613