Title :
Optimization of the area/robustness/speed trade-off in a 28 nm FDSOI latch based on ULP diodes
Author :
Haine, Thomas ; Stas, Francois ; Bol, David
Author_Institution :
Ecole Polytech. de Louvain, Univ. Catholique de Louvain, Louvain-la-Neuve, Belgium
Abstract :
Ultra-low-power (ULP) diodes are special 2-T structures featuring a unique negative-differential resistance characteristic that can be used to build a 4-T ULP latch for flip-flop or SRAM applications. In this paper, we explore the area/mismatch tradeoff in such a ULP latch for ultra-low-voltage (ULV) SoCs in 28 nm FDSOI CMOS. We analyze the impact of transistor sizing, supply voltage and back-gate biasing to reach 6¿ robustness of the latch against mismatch while maintaining a leakage power below 10 pW. Under these constraints, the use of a genetic algorithm allows us to obtain the Pareto curve of optimal solutions between area and speed for both flip-flop and SRAM applications.
Keywords :
CMOS logic circuits; CMOS memory circuits; SRAM chips; circuit optimisation; flip-flops; genetic algorithms; integrated circuit design; integrated circuit reliability; low-power electronics; semiconductor diodes; silicon-on-insulator; 2-T structure; FDSOI CMOS; FDSOI latch; Pareto curve; SRAM application; ULP diode; area-robustness-speed trade-off; back gate biasing; flip-flop application; genetic algorithm; negative differential resistance characteristic; size 28 nm; supply voltage; system-on-chips; transistor sizing; ultralow power diode; ultralow voltage SoC; Genetics; Junctions; Latches; Logic gates; MOS devices; Random access memory; Robustness; CMOS integrated circuits; SRAM; diode; flip-flop; latch; low leakage; low power; low voltage; memory;
Conference_Titel :
Faible Tension Faible Consommation (FTFC), 2014 IEEE
Conference_Location :
Monaco
DOI :
10.1109/FTFC.2014.6828614
