Title :
Energy-efficient logic and SRAM design: A case study
Author :
Reynders, Nele ; Rooseleer, Bram ; Dehaene, Wim
Author_Institution :
ESAT-MICAS, KU Leuven, Leuven, Belgium
Abstract :
This paper discusses energy-efficient design, both for logic and for memories. For datapaths which are controlled by dynamic energy, high energy-efficiency can be obtained by significantly reducing the supply voltage. However, simply lowering VDD does not automatically imply more energy-efficient operation for SRAM memories, as they are dominated by static leakage. This paper identifies which design methodologies can be employed to achieve high energy-efficiency. In particular, a JPEG encoder fabricated in a 40nm CMOS technology is used as a case study to determine the trade-offs, challenges and benefits of energy-efficient design.
Keywords :
CMOS logic circuits; CMOS memory circuits; SRAM chips; integrated circuit design; logic design; CMOS technology; JPEG encoder; SRAM design; datapaths; dynamic energy; energy-efficient logic design; size 40 nm; static leakage; supply voltage reduction; CMOS integrated circuits; Energy consumption; Latches; Logic gates; Quantization (signal); Random access memory; Transform coding;
Conference_Titel :
Faible Tension Faible Consommation (FTFC), 2014 IEEE
Conference_Location :
Monaco
DOI :
10.1109/FTFC.2014.6828616
