DocumentCode :
1507633
Title :
Low temperature and low cost planarised aluminium interconnect for sub-half micrometre VLSI circuits
Author :
Zhao, B. ; Biberger, M.A. ; Hoffman, V. ; Wang, S.Q. ; Vasudev, P.K. ; Seidel, T.E.
Author_Institution :
SEMATECH, Austin, TX, USA
Volume :
33
Issue :
3
fYear :
1997
fDate :
1/30/1997 12:00:00 AM
Firstpage :
247
Lastpage :
248
Abstract :
Planarised Al interconnect structures for sub-half micrometre integrated circuits have been fabricated by a novel low temperature and low pressure sputtering deposition technique. Simultaneous high aspect ratio interconnect hole fill and metal layer planarisation were achieved with moderate heat applied to processed wafers during the Al deposition. Low via resistance (~1 Ω for 0.35 μm vias) and high via chain yield (~100%) have been obtained on the wafers processed at a wafer temperature of 380°C
Keywords :
VLSI; aluminium; integrated circuit interconnections; integrated circuit metallisation; sputter deposition; 0.35 micron; 380 degC; Al; aspect ratio; interconnect hole fill; metal layer planarisation; planarised interconnect; sputtering deposition technique; sub-half micrometre VLSI circuits; via chain yield; via resistance; wafer temperature;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:19970165
Filename :
575964
Link To Document :
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