Title :
Optimal scheduling of signature analysis for VLSI testing
Author :
Lee, Y.-H. ; Krishna, C.M.
Author_Institution :
Dept. of Comput. & Inf. Sci., Florida Univ., Gainesville, FL, USA
fDate :
3/1/1991 12:00:00 AM
Abstract :
A simple algorithm that shows how to optimally schedule the test-application and the signature-analysis phases of VLSI testing is presented. The testing process is broken into subintervals, the signature is analyzed at the end of each subinterval, and future tests are aborted if the circuit is found to be faulty, thus saving test time. The mathematical proofs associated with the algorithm are given
Keywords :
VLSI; integrated circuit testing; logic testing; scheduling; VLSI testing; mathematical proofs; optimal scheduling; signature analysis; subintervals; test-application; Algorithm design and analysis; Application software; Circuit faults; Circuit testing; Councils; Job shop scheduling; Optimal scheduling; Pattern analysis; Scheduling algorithm; Very large scale integration;
Journal_Title :
Computers, IEEE Transactions on
