DocumentCode
1508513
Title
A Floating-Body/Gate DRAM Cell Upgraded for Long Retention Time
Author
Lu, Zhichao ; Fossum, Jerry G. ; Zhou, Zhenming
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL, USA
Volume
32
Issue
6
fYear
2011
fDate
6/1/2011 12:00:00 AM
Firstpage
731
Lastpage
733
Abstract
A novel modification of our “2T” floating-body/gate DRAM cell is described and, via numerical simulations, shown to yield very long charge data retention times under worst-case conditions, as well as good memory performance (i.e., large signal margin and low operating power). Relatively low voltage operation is enabled, thereby implying good cell reliability as well.
Keywords
random-access storage; 2T floating-body/gate DRAM cell; cell reliability; large signal margin; long retention time; low operating power; low voltage operation; memory performance; numerical simulation; Capacitance; Logic gates; Numerical simulation; Random access memory; Reliability; Semiconductor process modeling; Tunneling; Band-to-band tunneling; GIDL; capacitorless DRAM; floating-body effects; gated diode; memory reliability; silicon-on-insulator MOSFETs;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2011.2134065
Filename
5762320
Link To Document