Title :
Design of high speed high SNR bit-stream adder based on ΣΔmodulation
Author :
Liang, Yun ; Wang, Z.G. ; Meng, Qinghu ; Guo, X.D.
Author_Institution :
Inst. of RF- & OE-ICs, Southeast Univ., Nanjing, China
Abstract :
A bit-stream adder circuit based on sigma delta (ΣΔ) modulation is proposed and designed in the TSMC 0.18 μm CMOS process. The operating frequency and signal-to-noise ratio (SNR) performance were verified through simulation in Hspice and Matlab. The simulation results show that the proposed circuit can work at a frequency of higher than 10 GHz. Compared with conventional bit-stream adder circuits, the proposed circuit can achieve much better SNR performance or the same SNR performance with several times higher operating frequency and about 20% hardware saving.
Keywords :
CMOS digital integrated circuits; adders; sigma-delta modulation; Σδ modulation; CMOS process; Hspice simulation; Matlab; bit-stream adder circuit; operating frequency; sigma delta modulation; signal-to-noise ratio; size 0.18 mum; speed high SNR bit-stream adder design;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2010.0153
