A High-Reliability, Low-Power Magnetic Full Adder

Author

Gang, Yi ; Zhao, Weisheng ; Klein, Jacques-Olivier ; Chappert, Claude ; Mazoyer, Pascale

Author_Institution

IEF, Univ. Paris-Sud, Orsay, France

Volume

47

Issue

11

fYear

2011

Firstpage

4611

Lastpage

4616

Abstract

Recently, ultra-low power circuits based on logic-in magnetic tunnel junction (MTJ) memory structure have been studied thanks to its non-volatility, infinite endurance, high access speed, and easy integration with CMOS process. However, this type of circuit suffers from low reliability both in memory cell and sensing amplifier circuits, which greatly limits its practical applications for logic computation. In this paper, we present a new design of magnetic full adder (MFA) to overcome this issue based on the thermally assisted switching (TAS) MTJ cell and pre-charge sensing amplifier (PCSA) circuit. By using CMOS 65 nm design kit and a precise TAS-MTJ model, mixed simulations have been performed to demonstrate its high reliability keeping low power and small die area.

Keywords

CMOS integrated circuits; adders; amplifiers; integrated circuit modelling; integrated circuit reliability; logic circuits; magnetic tunnelling; CMOS process; high access speed; high-reliability adder; infinite endurance; logic-in magnetic tunnel junction; low-power magnetic full adder; memory cell; memory structure; pre-charge sensing amplifier circuit; sensing amplifier circuits; size 65 nm; thermally assisted switching; ultralow power circuits; Adders; CMOS integrated circuits; Integrated circuit reliability; Magnetic tunneling; Switches; Tunneling magnetoresistance; Full adder; high reliability; low power; magnetic circuits; magnetic full adder; magnetic tunnel junction; pre-charge sensing amplifier;

fLanguage

English

Journal_Title

Magnetics, IEEE Transactions on

Publisher

ieee

ISSN

0018-9464

Type

jour

DOI

10.1109/TMAG.2011.2150238

Filename

5762606