A 10 Gb/s hybrid-integrated receiver array module using a planar lightwave circuit (PLC) platform including a novel assembly region structure

Author

Mino, Shinji ; Ohyama, Takaharu ; Akahori, Yuji ; Hashimoto, Toshikazu ; Yamada, Yasufumi ; Yanagisawa, Masahiro ; Muramoto, Yoshifumi

Author_Institution

NTT Opto-Electron. Labs., Ibaraki, Japan

Volume

14

Issue

11

fYear

1996

fDate

11/1/1996 12:00:00 AM

Firstpage

2475

Lastpage

2482

Abstract

A planar lightwave circuit (PLC) platform for optoelectronic hybrid integration shows potential for achieving 10 Gb/s operation. It uses AuSn bump-type bonding pads on a silica layer to decrease parasitic capacitance, which limited the CR time constant in the optical chip assembly region, and two-layer electrical wiring to reduce parasitic inductance, which caused resonance in the electrical circuit region. An arrayed receiver module fabricated by integrating a two-channel monolithic opto-electronic integrated circuit (OEIC) chip on the PLC platform demonstrated a 3 dB-bandwidth of 8 GHz in both channels, which is equal to the bandwidth of the OEIC chip. This shows the feasibility of using this PLC platform for multichannel 10 Gb/s operation. Furthermore, this PLC platform can combine the versatile optical circuit functions of a PLC, such as an arrayed-waveguide grating wavelength multiplexer, with the high-speed signal processing function of mature electronic IC circuits. Consequently, this platform is a key device that will lead to high-capacity optical signal processing systems using optical wavelength/frequency routing

Keywords

digital communication; hybrid integrated circuits; integrated circuit interconnections; integrated circuit packaging; integrated optoelectronics; microassembling; modules; optical receivers; soldering; 10 Gbit/s; 8 GHz; AuSn; AuSn bump-type bonding pads; SiO₂; arrayed-waveguide grating wavelength multiplexer; assembly region structure; high-capacity optical signal processing systems; high-speed signal processing function; hybrid-integrated receiver array module; optical wavelength/frequency routing; optoelectronic integrated circuit; parasitic capacitance reduction; parasitic inductance reduction; planar lightwave circuit platform; silica layer; two-channel OEIC chip; two-layer electrical wiring; Bonding; Circuits; High speed optical techniques; Optical arrays; Optical receivers; Optical signal processing; Optoelectronic devices; Parasitic capacitance; Programmable control; Silicon compounds;

fLanguage

English

Journal_Title

Lightwave Technology, Journal of

Publisher

ieee

ISSN

0733-8724

Type

jour

DOI

10.1109/50.548144

Filename

548144