A dual-phase-controlled dynamic latched amplifier for high-speed and low-power DRAMs

Author

Fujisawa, Hiroki ; Takahashi, Tsugio ; Nakamura, Masayuki ; Kujigaya, K.

Author_Institution

Dev. Div., Elpida Memory Inc., Kanagawa, Japan

Volume

36

Issue

7

fYear

2001

fDate

7/1/2001 12:00:00 AM

Firstpage

1120

Lastpage

1126

Abstract

A dual-phase-controlled dynamic latched (DDL) amplifier for a differential data transfer scheme designed to achieve both high speed and low power in DRAMs is described. This circuit reduces the excessive operating margin caused by device fluctuations by using a pair of dynamic latched amplifiers, controlled by a dual-phase clock, to automatically correct the output data. Two circuit technologies are used in the DDL amplifier to achieve 200-MHz operation in a 1-Gb SDRAM using 0.13-μm technology: a cycle-time-progressive control circuit that increases the operating frequency and a shared DDL amplifier technique that reduces the area penalty of the DDL amplifier. These techniques and circuits reduce the access time to 10 ns, which is 1.2 ns less than that of the conventional dynamic amplifier, while also reducing the operating current to less than 10% that of the static amplifier

Keywords

CMOS memory circuits; DRAM chips; differential amplifiers; error correction; high-speed integrated circuits; low-power electronics; 0.13 micron; 1 Gbit; 10 ns; 200 MHz; SDRAM; access time reduction; cycle-time-progressive control circuit; differential data transfer scheme; dual phase control; dual-phase clock; dynamic latched amplifier; high-speed DRAMs; low-power DRAMs; operating current reduction; shared DDL amplifier technique; synchronous DRAM; Circuits; Delay effects; Differential amplifiers; Energy consumption; Fluctuations; Frequency; High power amplifiers; Operational amplifiers; Random access memory; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.933470

Filename

933470