Title :
Configurations for IDDQ-testable PLAs
Author :
Sachdev, Manoj ; Kerkhoff, Hans
Author_Institution :
Waterloo Univ., Ont., Canada
Abstract :
In these two PLA configurations, adjacent precharge lines activate, and adjacent evaluation lines evaluate, to complementary logic levels. This design-for-test technique makes it possible to use IDDQ tests to defect all likely bridging faults-for the most part independently of the PLA´s implemented function
Keywords :
logic testing; programmable logic arrays; IDDQ tests; PLA; PLA configurations; bridging faults; complementary logic levels; design-for-test; evaluation lines; precharge lines; CMOS logic circuits; Clocks; Fault detection; Logic arrays; Logic design; Logic testing; Programmable logic arrays; Semiconductor device modeling; Turning; Variable structure systems;
Journal_Title :
Design & Test of Computers, IEEE
