Some space considerations of VLSI systolic array mappings

In this brief, the space-time mapping of the dependency matrix of an algorithm is used to study spatial properties of a systolic array implementation of a three-nested loop structure. Elementary expressions are developed for both the number of processing elements and the area of the array. These expressions involve only the space-time transformation and the lengths of the loops. As well, characterizations have been found for the form of the space-time transformation which produces a systolic array with the minimum number of processing elements, and one which has both the minimum number of processing elements and the smallest area. Moreover, the approaches can also be extended to general algorithms, such as variable loop lengths