• DocumentCode
    15106
  • Title

    Automated Design Error Localization in RTL Designs

  • Author

    Jenihhin, Maksim ; Tsepurov, Anton ; Tihhomirov, Valentin ; Raik, Jaan ; Hantson, Hanno ; Ubar, Raimund ; Bartsch, Gunter ; Escobar, JorgeHernan Meza ; Wuttke, Heinz-Dietrich

  • Author_Institution
    Dept. of Comput. Eng., Tallinn Univ. of Technol., Tallinn, Estonia
  • Volume
    31
  • Issue
    1
  • fYear
    2014
  • fDate
    Feb. 2014
  • Firstpage
    83
  • Lastpage
    92
  • Abstract
    This paper considers the case where a design described in a Hardware Description Language (HDL) has been identified as erroneous during functional verification and, thus, design error localization is required. However, due to the enormous complexity of modern Register-Transfer Level (RTL) designs, several bugs may escape verification and are consequently handled by post-silicon validation.
  • Keywords
    formal verification; hardware description languages; HDL; RTL designs; automated design error localization; functional verification; hardware description language; post-silicon validation; register transfer level; Computer bugs; Design methodology; Error analysis; Hardware design languages; Registers; Verification;
  • fLanguage
    English
  • Journal_Title
    Design & Test, IEEE
  • Publisher
    ieee
  • ISSN
    2168-2356
  • Type

    jour

  • DOI
    10.1109/MDAT.2013.2271420
  • Filename
    6549113
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=15106