The cache DRAM architecture: a DRAM with an on-chip cache memory

Author

Hidaka, Hideto ; Matsuda, Yoshio ; Asakura, Mikio ; Fujishima, Kazuyasu

Author_Institution

Mitsubishi Electr. Corp., Itami, Japan

Volume

10

Issue

2

fYear

1990

fDate

4/1/1990 12:00:00 AM

Firstpage

14

Lastpage

25

Abstract

A DRAM (dynamic RAM) with an on-chip cache, called the cache DRAM, has been proposed and fabricated. It is a hierarchical RAM containing a 1-Mb DRAM for the main memory and an 8-kb SRAM (static RAM) for cache memory. It uses a 1.2- mu m CMOS technology. Suitable for no-wait-state memory access in low-end workstations and personal computers, the chip also serves high-end systems as a secondary cache scheme. It is shown how the cache DRAM bridges the gap in speed between high-performance microprocessor units and existing DRAMs. The cache DRAM concept is explained, and its architecture is presented. The error checking and correction scheme used to improve the cache DRAM´s reliability is described. Performance results for an experimental device are reported.<>

Keywords

CMOS integrated circuits; buffer storage; integrated memory circuits; random-access storage; 1 Mbit; 1-Mb DRAM; 1.2- mu m CMOS technology; 8 kbit; 8-kb SRAM; cache DRAM; cache memory; correction; dynamic RAM; error checking; hierarchical RAM; high-performance microprocessor units; no-wait-state memory access; on-chip cache; static RAM; Bridges; CMOS technology; Cache memory; Computer architecture; DRAM chips; Microcomputers; Microprocessors; Random access memory; Read-write memory; Workstations;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/40.52944

Filename

52944