A time-delay digital tanlock loop

Author

Hussain, Zahir M. ; Boashash, Boualem ; Hassan-Ali, Mudhafar ; Al-Araji, Saleh R.

Author_Institution

Signal Process. Res. Centre, Queensland Univ. of Technol., Brisbane, Qld., Australia

Volume

49

Issue

8

fYear

2001

fDate

8/1/2001 12:00:00 AM

Firstpage

1808

Lastpage

1815

Abstract

We propose a nonuniform sampling digital tanlock loop (DTL) that utilizes a constant time-delay unit instead of the constant 90° phase shifter The new structure reduces the complexity of implementation and avoids many of the practical problems associated with the digital Hilbert transformer like the approximations and frequency limitations. The time-delay digital tanlock loop (TDTL) preserves the most important features of the conventional DTL (CDTL), such as reduced sensitivity to the variation of the signal power. It also introduces improvement over the first-order CDTL under suitable choice of the circuit parameters. The first- and second-order loops are analyzed for locking conditions and steady-state phase error

Keywords

clocks; delay lock loops; digital filters; oscillators; phase detectors; DC-free conditions; DPLL; circuit parameters; constant time-delay unit; convergence behavior; digital clock; digital controlled oscillator; digital loop filter; digital phase-locked loops; first-order CDTL; first-order loop; implementation complexity reduction; locking conditions; noise-free conditions; nonuniform sampling digital tanlock loop; performance analysis; phase error detector; reduced sensitivity; samplers; second-order loop; signal power variation; steady-state phase error; time-delay digital tanlock loop; time-delay unit; Circuit synthesis; Control system synthesis; Filtering; Frequency synthesizers; Nonuniform sampling; Phase locked loops; Phase shifters; Phase transformers; Signal synthesis; Steady-state;

fLanguage

English

Journal_Title

Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1053-587X

Type

jour

DOI

10.1109/78.934151

Filename

934151