Comparison of the Susceptibility to Soft Errors of SRAM-Based FPGA Error Correction Codes Implementations

Nowadays the reliability issues of SRAM-based Field Programmable Gate Arrays (FPGAs) operating in harsh environments are well understood. One major effect is Single Event Upsets (SEUs), which are able to invert the stored logical value in flip-flops and memory cells. This issue is more serious when the affected memory cells are part of the configuration memory used for programming the circuit functionality. The consequences may be alterations of the circuit functionality causing errors which may only be corrected by reprogramming the device. For a better understanding of the robustness of programmed circuits, this paper compares two decoders for Error Correction Codes (ECCs). A Hamming Decoder and a One-Step Majority Logic Decoder (OS-MLD) for the Difference-Set Cyclic Codes (DSCC) are analyzed yielding surprisingly unexpected results for their SEU susceptibility, which are interesting for application designers.