DocumentCode :
1511611
Title :
A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing
Author :
Chu, Chris C N ; Wong, D.F.
Author_Institution :
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
Volume :
18
Issue :
6
fYear :
1999
fDate :
6/1/1999 12:00:00 AM
Firstpage :
787
Lastpage :
798
Abstract :
In this paper, we present a completely new approach to the problem of delay minimization by simultaneous buffer insertion and wire sizing for a wire. We show that the problem can be formulated as a convex quadratic program, which is known to be solvable in polynomial time. Nevertheless, we explore some special properties of our problem and derive an optimal and very efficient algorithm, modified active set method (MASM), to solve the resulting program. Given m buffers and a set of m discrete choices of wire width, the running time of our algorithm is O(mn2) and is independent of the wire length in practice. For example, an instance of 100 buffers and 100 choices of wire width can be solved in 0.92 s. In addition, we extend MASM to consider simultaneous buffer insertion, buffer sizing, and wire sizing. The resulting algorithm MASM-BS is again optimal and very efficient. For example, with six choices of buffer size and 10 choices of wire width, the optimal solution for a 15000 μm long wire can be found in 0.05 s. Besides, our formulation is so versatile that it is easy to consider other objectives like wire area or power dissipation, or to add constraints to the solution. Also, wire capacitance lookup tables, or very general wire capacitance models which can capture area capacitance, fringing capacitance, coupling capacitance, etc. can be used
Keywords :
buffer circuits; circuit layout CAD; circuit optimisation; delays; integrated circuit interconnections; integrated circuit layout; minimisation; quadratic programming; table lookup; MASM-BS; buffer insertion/sizing; convex quadratic program; delay minimization; modified active set method; polynomial time solution; power dissipation; quadratic programming; simultaneous buffer insertion/wire sizing; wire area; wire capacitance lookup tables; wire capacitance models; wire sizing; Capacitance; Delay effects; Integrated circuit interconnections; Minimization; Polynomials; Power dissipation; Quadratic programming; Table lookup; Very large scale integration; Wire;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.766728
Filename :
766728
Link To Document :
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