DocumentCode
1511714
Title
Universal delay test sets for logic networks
Author
Sparmann, Uwe ; Müller, Holger ; Reddy, Sudhakar M.
Author_Institution
Comput. Sci. Dept., Saarlandes Univ., Saarbrucken, Germany
Volume
7
Issue
2
fYear
1999
fDate
6/1/1999 12:00:00 AM
Firstpage
156
Lastpage
166
Abstract
It has been shown earlier that, if we are restricted to unate gate network (UGN) realizations, there exist universal test sets for Boolean functions. Such a test set only depends on the function f, and checks any UGN realization of f for all multiple stuck-at faults and all robustly testable stuck-open faults. In this paper, we prove that these universal test sets are much more powerful than implied by the above results. They also constitute complete delay fault test sets for arbitrary UGN implementations of a given function. This is even true for UGN networks which are not completely testable with respect to the gate or path delay fault model. Our ability to prove the temporal correctness of such circuit realizations comes from the fact that we do not argue the correctness of individual paths, but rather complete path systems.
Keywords
Boolean functions; VLSI; delays; design for testability; fault diagnosis; integrated circuit testing; logic testing; Boolean functions; circuit realizations; complete path systems; logic networks; multiple stuck-at faults; robustly testable stuck-open faults; temporal correctness; unate gate network; universal delay test sets; Boolean functions; Circuit faults; Circuit testing; Delay; Design for testability; Logic testing; Manufacturing; Power system modeling; Robustness; Very large scale integration;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/92.766742
Filename
766742
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