DocumentCode :
1511793
Title :
A multiple clocking scheme for low-power RTL design
Author :
Papachristou, Christos A. ; Nourani, Mehrdad ; Spining, Mark
Author_Institution :
Dept. of Electr. Eng., Case Western Reserve Univ., Cleveland, OH, USA
Volume :
7
Issue :
2
fYear :
1999
fDate :
6/1/1999 12:00:00 AM
Firstpage :
266
Lastpage :
276
Abstract :
This paper presents a resource allocation technique to design low-power register-transfer-level datapaths. The basis of this technique is to use a multiple clocking scheme of n nonoverlapping clocks, by dividing the frequency f of a single clock into n cycles, to partition the circuit into n disjoint modules and assign each module to a distinct clock, and to operate each module only during its corresponding duty cycle, thus clocking each module by a frequency f/n to reduce power. However, the overall effective frequency of the circuit remains f, i.e., the single clock frequency. Further power reduction is also obtained by tradeoffs between voltage, power, and delay across multiple clock partitions. Power savings up to 50% of the proposed multiple clocking scheme in comparison to single gated clock designs are also reported.
Keywords :
CMOS logic circuits; VLSI; clocks; logic CAD; logic partitioning; low-power electronics; resource allocation; disjoint modules; duty cycle; low-power RTL design; multiple clocking scheme; nonoverlapping clocks; power reduction; resource allocation technique; CMOS logic circuits; Clocks; Delay; Energy consumption; Frequency conversion; Logic programming; Power dissipation; Power supplies; Resource management; Voltage;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/92.766754
Filename :
766754
Link To Document :
بازگشت