Title :
Path metric memory management for minimising interconnections in Viterbi decoders
Author :
Kim, S.-Y. ; Kim, H. ; Park, I.-C.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
fDate :
7/5/2001 12:00:00 AM
Abstract :
To simplify the interconnection between processing elements and path metric memory banks in Viterbi decoders, a new path metric update scheme is proposed based on two techniques, named swapped state grouping and swapped computing. The proposed scheme leads to a simple interconnection consisting of 2×2 switches
Keywords :
CMOS digital integrated circuits; Viterbi decoding; digital signal processing chips; integrated circuit interconnections; minimisation; storage management; Viterbi decoders; interconnections minimisation; path metric memory management; path metric update scheme; swapped computing; swapped state grouping;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20010617
