Optimization of a self-aligned titanium silicide process for submicron technology

Author

Lévy, Didier ; Delpech, Philippe ; Paoli, Maryse ; Masurel, Claude ; Vernet, Michel ; Brun, Nicole ; Jeanne, Jean-Pierre ; Gonchond, Jean-Pierre ; Ada-Hanifi, Mohamed ; Haond, Michel ; D´Ouville, Thierry Ternisien ; Mingam, Hervé

Author_Institution

Bull, Les Clayes-sous-Bois, France

Volume

3

Issue

4

fYear

1990

fDate

11/1/1990 12:00:00 AM

Firstpage

168

Lastpage

175

Abstract

The optimization of a manufacturable self-aligned titanium silicide process is described. In particular, the integrity of the TiSi ₂ layer has been studied versus the BPSG reflow conditions. Excellent contact resistance and very low leakage currents have been obtained. The good device parameters obtained with an n⁺ or n ⁺/p⁺ gate have demonstrated that the self-aligned process can be integrated in a 0.8-μm double-metal CMOS process

Keywords

CMOS integrated circuits; contact resistance; integrated circuit manufacture; integrated circuit technology; leakage currents; metallisation; titanium compounds; 0.8 micron; B2O3-P2O5-SiO2; BPSG reflow conditions; IC fabrication; TiSi₂ layer; contact resistance; double-metal CMOS process; low leakage currents; manufacturable self-aligned process; n⁺ gate; n⁺/p⁺ gate; optimization; submicron technology; CMOS process; Conductivity; Furnaces; Manufacturing processes; Rapid thermal annealing; Semiconductor films; Silicides; Silicon; Surface contamination; Titanium;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.61965

Filename

61965