DocumentCode :
1512225
Title :
A fully parallel vector-quantization processor for real-time motion-picture compression
Author :
Nakada, Akira ; Shibata, Tadashi ; Konda, Masahiro ; Morimoto, Tatsuo ; Ohmi, Tadahiro
Author_Institution :
VLSI Design & Educ. Center, Tokyo Univ., Japan
Volume :
34
Issue :
6
fYear :
1999
fDate :
6/1/1999 12:00:00 AM
Firstpage :
822
Lastpage :
830
Abstract :
A vector-quantization (VQ) processor system has been developed aiming at real-time compression of motion pictures using a 0.6-μm triple-metal CMOS technology. The chip employs a fully parallel single-instruction, multiple-data architecture having a two-stage pipeline. Each pipeline segment consists of 19 cycles, thus enabling the execution of a single VQ operation in only 19 clock cycles. As a result, it has become possible to encode a full-color picture of 640×480 pixels in less than 33 ms, i.e., the real-time compression of moving pictures has become available. The chip is scalable up to eight-chip master-slave configuration in conducting fully parallel search for 2-K template vectors. The chip operates at 17 MHz with a power dissipation of 0.29 W under a power-supply voltage of 3.3 V
Keywords :
CMOS digital integrated circuits; data compression; digital signal processing chips; image coding; image motion analysis; parallel processing; pipeline processing; real-time systems; vector quantisation; 0.29 W; 0.6 micron; 17 MHz; 3.3 V; 480 pixel; 640 pixel; CMOS chip; SIMD architecture; master-slave configuration; parallel vector quantization processor; real-time motion picture compression; two-stage pipeline; CMOS technology; Clocks; Hardware; Image coding; Maximum likelihood decoding; Motion pictures; Pipelines; Power engineering and energy; Real time systems; Video compression;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/4.766816
Filename :
766816
Link To Document :
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