Title :
Miller and noise effects in a synchronizing flip-flop
Author :
Dike, Charles ; Burton, Edward
Author_Institution :
Intel Corp., Hillsboro, OR, USA
fDate :
6/1/1999 12:00:00 AM
Abstract :
The effects of Miller coupling and thermal noise on a synchronizing flip-flop are described. Data on the metastability characteristics of the flip-flop are gathered and analyzed. True metastability is distinguished from the deterministic region. A worst case mean-time-between-failure bound is established. A simple and accurate test method is presented. A simple jamb latch was used with driving circuits of two different strengths to determine the role of input strength on Tm and τ. The flip-flop was fabricated on a 0.25-μm CMOS process
Keywords :
CMOS logic circuits; flip-flops; integrated circuit noise; synchronisation; thermal noise; 0.25 micron; CMOS circuit; Miller coupling; jamb latch; mean-time-between-failure; metastability; synchronizing flip-flop; thermal noise; Capacitance; Circuit noise; Circuit testing; Clocks; Delay; Flip-flops; Frequency synchronization; Histograms; Latches; Metastasis;
Journal_Title :
Solid-State Circuits, IEEE Journal of
