AC product defect level and yield loss

Author

Savir, Jacob

Author_Institution

IBM Data Syst. Div., Poughkeepsie, NY, USA

Volume

3

Issue

4

fYear

1990

fDate

11/1/1990 12:00:00 AM

Firstpage

195

Lastpage

205

Abstract

The AC defect level and yield loss after test for both logic and random-access memory (RAM) semiconductor chips is considered. Computation of chip AC defect level and yield loss, after test, is dependent upon the availability of statistical information regarding the behavior of the chip´s delay and of the test error. This statistical information can either be derived from manufacturing process parameters or measured by a tester. The tester accuracy and the test coverage in computing the AC defect level and yield loss are taken into account

Keywords

integrated circuit manufacture; integrated circuit testing; integrated logic circuits; integrated memory circuits; logic testing; probability; production testing; random-access storage; statistical analysis; AC product defect level; RAM chips; logic chips; manufacturing process parameters; probability density function; random-access memory; semiconductor chips; statistical information; test coverage; tester accuracy; yield loss; Added delay; Automatic testing; Circuit faults; Circuit testing; Costs; Delay effects; Logic testing; Packaging; Random access memory; Semiconductor device testing;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.61969

Filename

61969