Current sensing differential logic: a CMOS logic for high reliability and flexibility

Author

Park, Joonbae ; Lee, Jeongho ; Kim, Wonchan

Author_Institution

Seoul Nat. Univ., South Korea

Volume

34

Issue

6

fYear

1999

fDate

6/1/1999 12:00:00 AM

Firstpage

904

Lastpage

908

Abstract

In this paper, we present a highly reliable and flexible CMOS differential logic called current sensing differential logic (CSDL). This CSDL eliminates the timing constraints between the enable signal and input signals, which cause difficulties in design with conventional differential logic families, by employing a simple clocking scheme. The power-delay product of CSDL is also reduced by using a swing suppression technique. To verify the reliability and the applicability of the proposed CSDL in large very large-scale-integration systems, a 64-bit carry-lookahead adder has been fabricated in a 0.6 μm CMOS technology. Experimental results show that the critical path delay is 3.5 ns with a power consumption of 27 mW at 50 MHz

Keywords

CMOS logic circuits; VLSI; adders; carry logic; integrated circuit reliability; sensitivity analysis; timing; 0.6 micron; 27 mW; 3.5 ns; 50 MHz; CMOS logic; CSDL; carry-lookahead adder; clocking scheme; current sensing differential logic; flexible CMOS differential logic; high reliability; large VLSI systems; power-delay product reduction; swing suppression technique; timing constraints elimination; very large-scale-integration; Acceleration; CMOS logic circuits; CMOS technology; Capacitance; Clocks; Delay; Driver circuits; Energy consumption; Pulse inverters; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.766829

Filename

766829