Title :
A Sixth-Order 200 MHz IF Bandpass Sigma-Delta Modulator With Over 68 dB SNDR in 10 MHz Bandwidth
Author :
Lu, Cho-Ying ; Silva-Rivas, Jose Fabian ; Kode, Praveena ; Silva-Martinez, Jose ; Hoyos, Sebastian
Author_Institution :
Electr. & Comput. Eng. Dept., Texas A&M Univ., College Station, TX, USA
fDate :
6/1/2010 12:00:00 AM
Abstract :
This paper presents a sixth-order bandpass ΣΔ modulator with 10 MHz bandwidth and 200 MHz center frequency suitable for high-IF applications. The fs/4 modulator employs an 800 MHz clock frequency and uses an active RC loop filter implemented with three-stage linearized operational amplifiers achieving more than 50 dB gain at 200 MHz. Furthermore, a calibration technique is proposed to compensate for process-voltage-temperature (PVT) variations, which involves measurement and optimization of the noise transfer function by injecting two auxiliary tones at the quantizer input. The modulator achieves 68.4 dB peak SNDR measured in 10 MHz bandwidth and IM3 of -73.5 dB at -2 dBr input signal. Fabricated in a vanilla 0.18 μm CMOS technology, the modulator consumes 160 mW (static + dynamic power) and occupies an active silicon area of 2.5 mm2.
Keywords :
CMOS analogue integrated circuits; operational amplifiers; sigma-delta modulation; CMOS technology; active RC loop filter; bandpass ΣΔ modulator; bandpass sigma-delta modulator; bandwidth 10 MHz; calibration technique; frequency 200 MHz; frequency 800 MHz; noise transfer function; operational amplifier; process-voltage-temperature variation; size 0.18 micron; Band pass filters; Bandwidth; CMOS technology; Calibration; Chirp modulation; Clocks; Delta-sigma modulation; Frequency; Gain; Operational amplifiers; Analog-to-digital converters; bandpass $SigmaDelta$ modulators; continuous-time modulators; high-IF ADCs; oversampling ADCs;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2010.2048505