DocumentCode
1512504
Title
A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS
Author
Tyshchenko, Oleksiy ; Sheikholeslami, Ali ; Tamura, Hirotaka ; Kibune, Masaya ; Yamaguchi, Hisakatsu ; Ogawa, Junji
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
Volume
45
Issue
6
fYear
2010
fDate
6/1/2010 12:00:00 AM
Firstpage
1091
Lastpage
1098
Abstract
This paper presents an ADC-based CDR that blindly samples the received signal at twice the data rate and uses these samples to directly estimate the locations of zero crossings for the purpose of clock and data recovery. We successfully confirmed the operation of the proposed CDR architecture at 5 Gb/s. The receiver is implemented in 65 nm CMOS, occupies 0.51 mm2, and consumes 178.4 mW at 5 Gb/s.
Keywords
CMOS digital integrated circuits; analogue-digital conversion; clock and data recovery circuits; ADC-based feedforward CDR; CMOS; bit rate 5 Gbit/s; clock and data recovery; power 178.4 mW; size 65 nm; zero crossings; Analog circuits; Clocks; Decision feedback equalizers; Digital signal processing; Feedforward systems; Integrated circuit technology; Sampling methods; Signal sampling; Transceivers; Voltage-controlled oscillators; ADC-based CDR; CDR; Clock and data recovery; all-digital CDR; blind-sampling CDR; feed-forward CDR;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.2010.2047156
Filename
5482524
Link To Document