High-performance cell transistor design using metallic shield embedded shallow trench isolation (MSE-STI) for Gbit generation DRAM´s

In this paper, the cell transistor design issues for the Gbit level DRAM´s with the isolation pitch of less than 0.2 μm caused by the inverse-narrow-channel effect (INCE) and the neighboring storage-node E-field penetration effect (NSPE) will be discussed. Then we propose novel DRAM cell transistor structure by employing metallic shield inside the shallow trench isolation (STI). As confirmed by three-dimensional (3-D) device simulation results, by suppressing the inverse narrow-channel effect and the neighboring storage-node E-field penetration effect using metallic shield inside STI, we can obtain reliable cell transistors with low-doped substrate, low junction leakage current and uniform V_TH a distribution regardless of the active width variation