A rule-based VLSI process flow validation system with macroscopic process simulation

As the integration scale of very large-scale integration (VLSI) circuits increases, it is becoming increasingly difficult to design long and complex process flows because there is a great amount of knowledge required in VLSI process technology. To assist in process-flow design, a rule-based validation system has been developed. This system checks designed process flows by using process knowledge related to contamination, cleaning methods, and the various constraints between the wafer structure and the process or equipment. It can point out error conditions that lead to such destructive results as contamination of the process equipment. The system applies process knowledge, expressed as if/then rules, to the process conditions and to macroscopic wafer structures derived from rule-based simulation. Due to the complexity of VLSI multilayered structures, information related to wafer structure is very important. This information can be obtained by rule-based simulation of such various macroscopic attributes of wafer structure as substance, contamination, and layer thickness. The validation system can precisely check various process flows and substantially improve the efficiency and quality of process-flow design