Title :
Applied Boolean equivalence verification and RTL static sign-off
Author_Institution :
Hewlett-Packard Co., Richardson, TX, USA
Abstract :
The author explores applying formal Boolean equivalence verification to the RTL design flow, and introduces an effective equivalence-checking usage model that ensures optimal benefits in an RTL static sign-off methodology
Keywords :
Boolean functions; formal verification; logic design; RTL static sign-off; applied Boolean equivalence verification; equivalence-checking usage model; formal Boolean equivalence verification; Automatic test pattern generation; Binary decision diagrams; Boolean functions; Circuit faults; Combinational circuits; Data structures; Flip-flops; Formal verification; Joining processes; Testing;
Journal_Title :
Design & Test of Computers, IEEE
