• DocumentCode
    1513458
  • Title

    Applied Boolean equivalence verification and RTL static sign-off

  • Author

    Foster, Harry

  • Author_Institution
    Hewlett-Packard Co., Richardson, TX, USA
  • Volume
    18
  • Issue
    4
  • fYear
    2001
  • Firstpage
    6
  • Lastpage
    15
  • Abstract
    The author explores applying formal Boolean equivalence verification to the RTL design flow, and introduces an effective equivalence-checking usage model that ensures optimal benefits in an RTL static sign-off methodology
  • Keywords
    Boolean functions; formal verification; logic design; RTL static sign-off; applied Boolean equivalence verification; equivalence-checking usage model; formal Boolean equivalence verification; Automatic test pattern generation; Binary decision diagrams; Boolean functions; Circuit faults; Combinational circuits; Data structures; Flip-flops; Formal verification; Joining processes; Testing;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.936244
  • Filename
    936244
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1513458