A Unified Method for Calculating Capacitive and Resistive Coupling Exploiting Geometry Constraints on Lightly and Heavily Doped CMOS Processes

Author

Bontzios, Yiorgos I. ; Hatzopoulos, Alkis A.

Author_Institution

Dept. of Electr. & Comput. Eng., Aristotle Univ. of Thessaloniki, Thessaloniki, Greece

Volume

57

Issue

8

fYear

2010

Firstpage

1751

Lastpage

1760

Abstract

A method for calculating capacitive and resistive coupling is developed in this work, and its implementation in commonly encountered practical cases is presented. The method is based on the geometry of the coupling mechanism, and the derived model is therefore, in general, scalable and technology independent. The constraints of any related problem can easily be incorporated into this method, whereas pure 3-D effects, such as capacitive coupling, are fast and accurately computed. The proposed method is validated using measurements from a test chip in the UMC 0.18- μm CMOS lightly doped process, simulation data obtained by two commercial simulators, and theoretical results. The accuracy of the method is shown to be within 2%-10%.

Keywords

CMOS integrated circuits; semiconductor doping; capacitive coupling; geometry constraints; heavily doped CMOS processes; lightly doped CMOS processes; resistive coupling; size 0.18 mum; CMOS process; CMOS technology; Circuit simulation; Computational modeling; Coupling circuits; Geometry; Integrated circuit modeling; Optical coupling; Semiconductor device modeling; Solid modeling; CMOS integrated circuits; geometric modeling; integrated circuit noise; substrate coupling;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2010.2050112

Filename

5483118