DocumentCode
1513587
Title
Pipeline direct digital frequency synthesiser using decomposition method
Author
Liu, S.-I. ; Yu, T.-B. ; Tsao, H.W.
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
148
Issue
3
fYear
2001
fDate
6/1/2001 12:00:00 AM
Firstpage
141
Lastpage
144
Abstract
A direct digital frequency synthesiser using a new decomposition method without the large sine ROM table is presented. To improve its operating frequency a pipeline structure has been utilised. It has been fabricated in a 0.6 μm single-poly double-metal (SPDM) CMOS process and its core area is 0.95×1.1 mm2. The maximum operating frequency is 85 MHz. For a 10 MHz sinusoidal output, the phase noise is -114 dBc/Hz at an offset frequency of 10 kHz. The measured SNR is 60.77 dB and worst case spurious is -67.6 dBc. Its power dissipation is 80 mW at 80 MHz under the 5 V supply
Keywords
CMOS digital integrated circuits; direct digital synthesis; phase noise; pipeline processing; 0.6 micron; 5 V; 80 mW; 85 MHz; SNR; core area; decomposition method; maximum operating frequency; offset frequency; operating frequency; phase noise; pipeline direct digital frequency synthesiser; power dissipation; single-poly double-metal CMOS process; worst case spurious;
fLanguage
English
Journal_Title
Circuits, Devices and Systems, IEE Proceedings -
Publisher
iet
ISSN
1350-2409
Type
jour
DOI
10.1049/ip-cds:20010158
Filename
936337
Link To Document