New path balancing algorithm for glitch power reduction

The authors propose an efficient path balancing algorithm to reduce glitch power dissipation in CMOS logic circuits. The proposed algorithm employs gate sizing and buffer insertion methods to achieve path balancing. The gate sizing technique reduces not only glitches, but also the effective capacitance in the circuit. For the paths which remain unbalanced after gate sizing due to the limitation of gate size, buffer insertion is performed. Since the buffer itself consumes power, it is inserted between the gates where power reduction achieved by glitch reduction is larger than the power consumed by the inserted buffer. Determining the location of the inserted buffer is a difficult problem, because the power reduction achieved by an inserted buffer is closely related to the locations of the other inserted buffers. The ILP (integer linear program) has been employed to determine the locations of inserted buffers. The proposed algorithm has been tested on LGSSynth91 benchmark circuits. Experimental results show that 61.5% of glitch reduction and 30.4% of power reduction are achieved without increasing the critical path delay