DocumentCode :
1513759
Title :
Mechanical–Electrical Measurements and Relevant Test Structures for Sensing Interconnect Stress Effects in CMOS Technology
Author :
Blayac, Sylvain ; Rivero, C. ; Fornara, P. ; Lopez, L. ; Demange, Nicolas
Author_Institution :
Provence Microelectronics Center, Ecole de Mines de Saint-Étienne, Gardanne, France
Volume :
25
Issue :
4
fYear :
2012
Firstpage :
564
Lastpage :
570
Abstract :
For CMOS technology, the increase of interconnects metal density is responsible for heterogeneous mechanical stress fields in active regions of silicon. Coupled mechanical–electrical measurements are performed to evaluate the impact of stress at circuit and device levels. This mismatch originated by interconnects metal lines stress is measured through the use of piezoresistive test structures. Local mechanical stress can thus be monitored in a simple process control compatible approach.
Keywords :
CMOS technology; Piezoresistance; Resistors; Silicon; Stress; Stress measurement; CMOS technology; piezoresistivity; stress test structures;
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/TSM.2012.2198500
Filename :
6197744
Link To Document :
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