Title :
MOS C-V characterization of ultrathin gate oxide thickness (1.3-1.8 nm)
Author :
Choi, Chang-Hoon ; Goo, Jung-Suk ; Oh, Tae-young ; Yu, Zhiping ; Dutton, Robert W. ; Bayoumi, Amr ; Cao, Min ; Voorde, P.V. ; Vook, Dieter ; Diaz, C.H.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
fDate :
6/1/1999 12:00:00 AM
Abstract :
An equivalent circuit approach to MOS capacitance-voltage (C-V) modeling of ultrathin gate oxides (1.3-1.8 nm) is proposed. Capacitance simulation including polysilicon depletion is based on quantum mechanical (QM) corrections implemented in a two-dimensional (2-D) device simulator; tunneling current is calculated using a one-dimensional (1-D) Green´s function solver. The sharp decrease in capacitance observed for gate oxides below 2.0 nm in both accumulation and inversion is modeled using distributed voltage-controlled RC networks. The imaginary components of small-signal input admittance obtained from AC network analysis agree well with measured capacitance.
Keywords :
Green´s function methods; MIS devices; capacitance; equivalent circuits; semiconductor device models; tunnelling; 1.3 to 1.8 nm; MOS device; capacitance-voltage characteristics; equivalent circuit; one-dimensional Green function; polysilicon depletion; quantum mechanical model; small-signal admittance; tunneling current; two-dimensional simulation; ultrathin gate oxide; Admittance; Capacitance-voltage characteristics; Circuit simulation; Equivalent circuits; Green´s function methods; Quantum capacitance; Quantum mechanics; Tunneling; Two dimensional displays; Voltage;
Journal_Title :
Electron Device Letters, IEEE
