A High-Frequency Compensated Crosstalk and ISI Equalizer for Multi-Channel On-Chip Interconnect in 130-nm CMOS

In this paper, a high-frequency crosstalk compensation scheme for high speed multi-channel on-chip interconnect is proposed. In the proposed scheme, a zero is inserted to the aggressor branch of the crosstalk feed-forward equalizer, which compensates for the high-frequency crosstalk, resulting in reduced timing jitter and increased eye opening. In order to verify the proposed scheme, an eight-channel 10-mm on-chip interconnect is implemented in 130-nm CMOS process. Measurement results show that the proposed scheme effectively removes the high frequency crosstalk and achieves a data rate of 2.9 Gb/s at a bit-error-rate below . The power consumption of the proposed transceiver is about 1 mW which corresponds to an energy efficiency of 0.4 pJ/bit.