DocumentCode :
1514522
Title :
Optimized synthesis of concurrently checked controllers
Author :
Leveugle, Régis ; Saucier, Gabrièle
Author_Institution :
CSI Lab., Inst. Nat. Polytech. de Grenoble, France
Volume :
39
Issue :
4
fYear :
1990
fDate :
4/1/1990 12:00:00 AM
Firstpage :
419
Lastpage :
425
Abstract :
A method for introducing online test facilities in a controller with a very low overhead is presented. This online test consists of detecting illegal paths in the control flow graph. These illegal paths may be due either to permanent faults or to transient errors. The state code flow is compacted through polynomial division. An implicit justifying signature method is applied at the state code level and ensures identical signatures before each join mode of the control flow graph. The signatures are then independent of the path followed previously in the graph, and the comparison to reference data is greatly facilitated. This property is obtained by a state assignment, nearly without area overhead. The controllers can then be checked by signature analysis, either by a built-in monitor or by an external checker
Keywords :
concurrency control; fault tolerant computing; logic testing; signal processing; concurrently checked controllers; control flow graph; justifying signature; online test facilities; state assignment; state code flow; transient errors; Control system synthesis; Control systems; Flow graphs; Flowcharts; Hardware; Helium; Monitoring; Test facilities; Testing; Very large scale integration;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.54835
Filename :
54835
Link To Document :
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