Reduced area discrete-time down-sampling filter embedded with windowed integration samplers

A technique to implement a discrete-time (DT) sinc³ ↓2 filter for windowed integration samplers is proposed. The topology reduces the idle time of the integration capacitors at the expense of a small complexity overhead in the clock generation, thereby saving 33% of the die area compared to the currently existing topology. Circuit level simulations in 45 nm CMOS technology shows good agreement with the predicted behaviour obtained from the analysis.