• DocumentCode
    1515022
  • Title

    Dynamic-biased capacitor-free NMOS LDO

  • Author

    Giustolisi, G. ; Palumbo, Gaetano

  • Author_Institution
    Dipt. di Ing. Elettr. Elettron. e dei Sist., Univ. degli Studi di Catania, Catania, Italy
  • Volume
    45
  • Issue
    22
  • fYear
    2009
  • Firstpage
    1140
  • Lastpage
    1141
  • Abstract
    A low-voltage low drop-out (LDO) voltage regulator is proposed. It is based on an NMOS output stage and exploits dynamic biasing for obtaining low-voltage (1.2 V) and low drop-out (200 mV) features. It does not require any external compensation capacitor and is able to deliver 50 mA with capacitive loads up to 10 nF. The circuit topology is discussed and experimental results are given.
  • Keywords
    MOS integrated circuits; electric potential; network topology; voltage regulators; NMOS output stage; circuit topology; external compensation capacitor; low-voltage low drop-out voltage regulator; voltage 1.2 mV;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el.2009.1220
  • Filename
    5295351
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1515022