Title :
A Hardware Implementation of a Run-Time Scheduler for Reconfigurable Systems
Author :
Clemente, Juan Antonio ; Resano, Javier ; González, Carlos ; Mozos, Daniel
Author_Institution :
Comput. Archit. Dept., Univ. Complutense de Madrid, Madrid, Spain
fDate :
7/1/2011 12:00:00 AM
Abstract :
New generation embedded systems demand high performance, efficiency, and flexibility. Reconfigurable hardware can provide all these features. However, the costly reconfiguration process and the lack of management support have prevented a broader use of these resources. To solve these issues we have developed a scheduler that deals with task-graphs at run-time, steering its execution in the reconfigurable resources while carrying out both prefetch and replacement techniques that cooperate to hide most of the reconfiguration delays. In our scheduling environment, task-graphs are analyzed at design-time to extract useful information. This information is used at run-time to obtain near-optimal schedules, escaping from local-optimum decisions, while only carrying out simple computations. Moreover, we have developed a hardware implementation of the scheduler that applies all the optimization techniques while introducing a delay of only a few clock cycles. In the experiments our scheduler clearly outperforms conventional run-time schedulers based on as-soon-as-possible techniques. In addition, our replacement policy, specially designed for reconfigurable systems, achieves almost optimal results both regarding reuse and performance.
Keywords :
embedded systems; multiprogramming; processor scheduling; reconfigurable architectures; storage management; clock cycles; hardware implementation; local-optimum decisions; near-optimal schedules; new generation embedded systems; prefetch techniques; reconfigurable systems; reconfiguration delays; replacement techniques; run-time scheduler; task-graphs; Clocks; Data mining; Delay; Embedded system; Hardware; Information analysis; Prefetching; Processor scheduling; Resource management; Runtime; Field-programmable gate arrays (FPGAs); reconfigurable architectures; task scheduling;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2010.2050158