DocumentCode :
1515419
Title :
Testing for coupled cells in random-access memories
Author :
Savir, J. ; McAnney, W.H. ; Vecchio, S.R.
Author_Institution :
IBM Data Syst. Div., Poughkeepsie, NY, USA
Volume :
40
Issue :
10
fYear :
1991
fDate :
10/1/1991 12:00:00 AM
Firstpage :
1177
Lastpage :
1180
Abstract :
Two test strategies for memory testing are compared for their ability to detect coupled-cell faults in an n-word-by-1-bit random access memory. In both strategies the data-in line is randomly driven. One of the two strategies uses random selection of both the address lines and the read/write control. The other strategy sequentially cycles through the address space with deterministic setting of the read/write control. The relative merit of the two strategies is measured by the average number of accesses per address needed to meet a standard test quality level
Keywords :
automatic testing; fault tolerant computing; integrated circuit testing; integrated memory circuits; random-access storage; RAM; address lines; address space; coupled-cell faults; deterministic setting; memory testing; random-access memories; read/write control; Art; Broadcasting; Computational efficiency; Couplings; Fault detection; Notice of Violation; Programming; Random access memory; Sorting; Testing;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.93752
Filename :
93752
Link To Document :
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