Analysis of branch handling strategies under hierarchical memory system

Branch instructions form a significant fraction of executed instructions in a computer program, and handling them is thus a crucial design issue for any architecture. In a hierarchical memory system, branch handling not only causes the pipeline drain but also results in more instructions being executed, which can result in a higher miss ratio. These phenomena are relevant to the resolution of the branch condition stage, the generation of branch target stage, and how the branch is handled. A new branch handling model to quantify the overall effects is developed. Eight kinds of branch handling strategies currently used are examined by this model. Tradeoffs among them can be made on a statistical and theoretical basis. Also, the results of prediction brought forth by this model among some architectures are compared with those of evaluation to justify this model.