100-Mbit/s single-chip Q-VLMS MLSE equalizer LSI for TDMA mobile radio communications

Author

Shirato, Yushi ; Kobayashi, Kiyoshi ; Denno, Satoshi

Author_Institution

NTT Network Innovation Labs., Kanagawa, Japan

Volume

36

Issue

8

fYear

2001

fDate

8/1/2001 12:00:00 AM

Firstpage

1178

Lastpage

1185

Abstract

A single-chip 100-Mbit/s burst-operation two-tap maximum likelihood sequence estimation (MLSE) equalizer LSI for QPSK signals is introduced. It also supports two-branch diversity combining. Three new techniques are used to realize this fast equalizer LSI: the quantized variable-gain least mean squares (VLMS) algorithm, which has small processing delay with fast convergence characteristics; a simple complex-valued multiplication scheme based on inverting the sign and switching the in-phase and quadrature-phase components; and a parallel structure to minimize the processing delay of path memory. The chip, containing 75 kgates, is manufactured using the 0.45-μm-CMOS gate array process. The supply voltage is 3.3 V. This LSI offers higher processing speed than any other conventional equalizer chip for mobile radio communications

Keywords

CMOS digital integrated circuits; adaptive equalisers; intersymbol interference; large scale integration; least mean squares methods; maximum likelihood sequence estimation; mobile radio; quadrature phase shift keying; time division multiple access; 100 Mbit/s; 3.3 V; CMOS gate array process; QPSK signals; TDMA mobile radio communication; burst-operation two-tap equalizer; complex-valued multiplication scheme; fast convergence characteristics; fast equalizer LSI; frequency selective fading; in-phase components; intersymbol interference; parallel structure; quadrature-phase components; quantized variable-gain LMS algorithm; single-chip Q-VLMS MLSE equalizer LSI; small processing delay; two-branch diversity combining; Convergence; Delay; Diversity reception; Equalizers; Large scale integration; Manufacturing processes; Maximum likelihood estimation; Quadrature phase shift keying; Time division multiple access; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.938368

Filename

938368