Asynchronous cross-pipelined multiplier

Author

Butas, Jan ; Choy, Chiu-Sing ; Povazanec, Juraj ; Chan, Cheong-Fat

Author_Institution

Dept. of Electr. Eng., Chinese Univ. of Hong Kong, Shatin, China

Volume

36

Issue

8

fYear

2001

fDate

8/1/2001 12:00:00 AM

Firstpage

1272

Lastpage

1275

Abstract

In this paper, a design of a 16-bit asynchronous multiplier is presented. The multiplier core consists of small basic blocks. Each block includes handshake and computation logic and communicates with four neighbor cells in asynchronous handshake fashion using four-phase protocol. The computation logic is implemented in dual-rail coded domino logic. The input and output signals of the multiplier are single-rail coded. The single-rail coding allows communication with other single-rail coded asynchronous blocks using four-phase signaling. The design speed is self-adjusting to the technology parameters and supply voltage variations. The multiplier has low latency and achieves a throughput rate of 250 MHz. The multiplier was fabricated in a 0.6-μm CMOS process and has a core size of 4.3×2.1 mm

Keywords

CMOS logic circuits; SPICE; asynchronous circuits; integrated circuit design; logic CAD; multiplying circuits; 16 bit; CMOS process; HSPICE; asynchronous cross-pipelined multiplier; asynchronous multiplier design; bit-parallel self-timed multiplier; computation logic; dual-rail coded domino logic; four-phase protocol; handshake logic; low latency; self-adjusting design speed; single-rail coded I/O signals; small basic blocks; Asynchronous circuits; Delay; Digital signal processing; Energy consumption; Logic circuits; Pipelines; Protocols; Signal design; Signal detection; Throughput;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.938377

Filename

938377