DocumentCode :
1516293
Title :
A 1 TB/s 1 pJ/b 6.4 
QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM
Author :
Miura, Noriyuki ; Saito, Mitsuko ; Kuroda, Tadahiro
Author_Institution :
Dept. of Electr. Eng., Keio Univ., Yokohama, Japan
Volume :
2
Issue :
2
fYear :
2012
fDate :
6/1/2012 12:00:00 AM
Firstpage :
249
Lastpage :
256
Abstract :
1 TB/s 1 pJ/b 6.4 mm2 /TB/s QDR inductive-coupling interface between 65-nm complementary metal-oxide-semicon ductor (CMOS) logic and emulated 100-nm dynamic random access memory (DRAM) is developed. BER <;10-10 operation is examined in 1024-bit parallel links. Compared to the latest wired 40-nm DRAM interface, the bandwidth is increased to 32×, and the energy consumption and the layout area are reduced to 1/8 and 1/22, respectively.
Keywords :
CMOS logic circuits; CMOS memory circuits; DRAM chips; error statistics; CMOS logic; DRAM; DRAM interface; QDR inductive-coupling interface; bit rate 1 Tbit/s; complementary metal-oxide-semiconductor logic; dynamic random access memory interface; energy consumption; parallel links; size 100 nm; size 65 nm; word length 1024 bit; CMOS integrated circuits; Clocks; Coils; MOS devices; Random access memory; Receivers; Transceivers; High-bandwidth interface; inductive coupling; memory-processor stacking; three-dimensional integration;
fLanguage :
English
Journal_Title :
Emerging and Selected Topics in Circuits and Systems, IEEE Journal on
Publisher :
ieee
ISSN :
2156-3357
Type :
jour
DOI :
10.1109/JETCAS.2012.2193836
Filename :
6199998
Link To Document :
