A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures

Author

Nandakumar, Vivek S. ; Marek-Sadowska, Malgorzata

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of California, Santa Barbara, CA, USA

Volume

2

Issue

2

fYear

2012

fDate

6/1/2012 12:00:00 AM

Firstpage

266

Lastpage

277

Abstract

In this paper, we study the network-on-chip (NoC) implemented with new vertical slit field effect transistors (VeSFETs). The unique properties of VeSFET circuits allow for very efficient power saving techniques that are not possible in complementary metal-oxide-semiconductor-based homogeneous 3-D NoCs. We demonstrate that the proposed 3-D hybrid architecture shows significant improvements in all network parameters including latency, power, and energy consumption compared to other practical 3-D NoCs.

Keywords

field effect transistors; multiprocessing systems; network-on-chip; power aware computing; 3D hybrid architecture; 3D multicore architectures; NoC; VeSFET circuits; complementary metal-oxide-semiconductor-based homogeneous 3D NoC; energy consumption; latency; low energy network-on-chip fabric; power saving techniques; vertical slit field effect transistors; Arrays; CMOS integrated circuits; Logic gates; Program processors; Throughput; Transistors; Wires; 3-D NoC; 3-D multi-core processsor; Memory on logic; network-on-chip (NoC); three-dimensional (3-D) integration; vertical slit field effect transistor (VeSFET); vertical slit transistor based integrated circuits (VeSTICs);

fLanguage

English

Journal_Title

Emerging and Selected Topics in Circuits and Systems, IEEE Journal on

Publisher

ieee

ISSN

2156-3357

Type

jour

DOI

10.1109/JETCAS.2012.2193834

Filename

6199999