Embedded trench DRAMs for sub-0.10-μm generation by using hemispherical-grain technique and LOCOS collar process

Author

Saida, Shigehiko ; Sato, Tsutomu ; Sato, Muneharu ; Kito, Masaru

Author_Institution

Adv. ULSI Process Eng. Dept. IV, Toshiba Corp., Kanagawa, Japan

Volume

14

Issue

3

fYear

2001

fDate

8/1/2001 12:00:00 AM

Firstpage

196

Lastpage

201

Abstract

For the future system on chip era, the embedded DRAM is one of the most important devices. Since the kinds of device increase and each device must be produced from only 10000 wafers, it is difficult to withdraw the investment cost to fabricate each device. To suppress the investment cost, the devices must be shrunk by changing the integration and the materials as little as possible. In this paper, we propose the trench capacitor scaling strategy. We show that the strategy achieves 30 fF/cell for the 0.08 μm trench and reduces the cost of ownership (COO) and raw process time (RPT) of the 0.08 μm trench to 80% of 0.18-μm trench, with an investment of only $1.6 M. It is achieved by the LOCOS collar process and HSG technique

Keywords

DRAM chips; VLSI; application specific integrated circuits; capacitance; isolation technology; large scale integration; 0.08 micron; HSG technique; LOCOS collar process; cost of ownership; embedded trench DRAMs; hemispherical-grain technique; investment cost; raw process time; system on chip era; trench capacitor scaling strategy; Capacitance; Capacitors; Costs; Doping; Investments; Large scale integration; Lithography; Logic devices; Random access memory; Ultra large scale integration;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.939812

Filename

939812