DocumentCode
1518348
Title
Aliasing probability for multiple input signature analyzer
Author
Pradhan, Dhiraj K. ; Gupta, Sandeep K. ; Karpovsky, Mark G.
Author_Institution
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Volume
39
Issue
4
fYear
1990
fDate
4/1/1990 12:00:00 AM
Firstpage
586
Lastpage
591
Abstract
Single and multiple multiple-input-signature-register (MISR) aliasing probability expressions are presented for arbitrary test lengths. A framework, based on algebraic codes, is developed for the analysis and synthesis of MISR-based test response compressors for BIST. This framework is used to develop closed-form expressions for the aliasing probability of MISR for arbitrary test length. An error model, based on q -ary symmetric channel, is proposed using more realistic assumptions. Results are presented that provide the weight distributions for q -ary codes (q =2m, where the circuit under test has m outputs). These results are used to compute the aliasing probability for the MISR compression technique for arbitrary test lengths. This result is extended to compression using two different MISRs. It is shown that significant improvements can be obtained by using two signature analyzers instead of one. The weight distribution of a class of codes of arbitrary length is also given
Keywords
logic analysers; algebraic codes; aliasing probability expressions; arbitrary test lengths; closed-form expressions; compression technique; error model; multiple input signature analyzer; multiple-input-signature-register; q-ary symmetric channel; test response compressors; weight distributions; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Digital circuits; Fault tolerance; Random variables; Redundancy; Reed-Solomon codes; Stochastic processes;
fLanguage
English
Journal_Title
Computers, IEEE Transactions on
Publisher
ieee
ISSN
0018-9340
Type
jour
DOI
10.1109/12.54855
Filename
54855
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